SPK286 an 80286 in synthesizable SystemVerilog

Bus status encoding

• After reset CS=F000 with hidden base FF0000 and IP=FFF0, so the first fetch is at FFFFF0.
• Address, status, BHE and write data hold while bus_valid && !ready.
• An odd word is two ordered cycles (N on D15:8, then N+1 on D7:0), each waiting for its own READY, with bus ownership kept between them.
• At a free boundary an accepted data request wins over code; once visible, a cycle keeps the bus until READY.
• HOLD is granted only at a free boundary and never splits an odd word, a locked read-modify-write or the INTA chain.
• Interrupt acknowledge is two READY-qualified INTA cycles; the vector is D7:0 of the second, and LOCK links both with the first stack push.
• Halt and shutdown are indicated with status 4 and address 2 or 0, without a READY-qualified transfer.

• Real-mode entry pushes FLAGS, CS and IP, clears IF and TF, reads the IVT, then commits CS:IP and flushes the queue in one step.
• No event is admitted inside a frame or a physical operand word.
• A frame push that cannot complete leads to double fault or shutdown, never to unbounded recursion.
• STI creates a one-instruction shadow only when IF goes from 0 to 1; MOV SS and POP SS inhibit interrupts for one instruction.

Observation without intrusion

spk286_timing_trace counts cycles, BIU busy time, READY waits, prefetch requests and responses, queue-empty cycles, redirects, operand waits and events. Unsupported policy requests fall back to 0 and set debug_timing_policy_error. The profiled variant is a generated drop-in copy of the top level; with historical_enable=0 it behaves as the functional core.

SingleStepTests/80286 as the functional oracle

The corpus was captured from a physical Harris N80C286-12 in real mode (pinned commit 37c73ca, MIT licence). Each MOO test is normalized, loaded into the RTL, run to one target retirement and compared on final registers and the whole sparse memory image, including neighbouring bytes. Undefined FLAGS bits are masked with the corpus masks.

MOO test -> normalized state -> RTL initialization -> one target retirement
         -> final registers and sparse RAM -> masked comparison

Every admitted case runs, including prefixed and exception-terminated ones. The 307 documented real-mode forms account for 1,386,996 cases; the rest cover SALC and the no-NPX 9B/D8 captures. Three cases are revoked upstream, and one record without a captured write strobe is reported as not evaluable — never as a pass.

Largest modules by LUTs

Hierarchy and all debug ports kept, so per-module figures are an upper bound. Multiply and divide are iterative and use no DSP blocks; the single M10K block holds the microcode ROM.

Instantiation

Instantiate spk286 from rtl/spk286.sv with the sources listed in scripts/rtl_sources.sh: the generated microcode package and ROMs first, then rtl/*.sv. rtl/timed/spk286_profiled.sv is a drop-in variant that adds the optional historical instruction-interval schedule.

Requirements: Verilator 5.020 or later, Icarus Verilog 12, Yosys, GNU make and Python 3 with the standard library only. On Ubuntu or WSL, make bootstrap installs them and make env checks them.

make regression        # microcode, lint, directed benches, Python tests, synthesis
make singlestep-fetch  # fetch the pinned SingleStepTests/80286 corpus
make singlestep        # run every supported SingleStep opcode file
make mutation-audit    # check that the benches reject injected RTL faults
make full-check        # everything, plus the profiled variant checks