Overview
A complete PC/XT, with two real video paths
The project implements classic PC/XT components as RTL logic running on the FPGA. Its goal is to reproduce the machine, its interfaces and its display timing, while leaving MiSTer to provide storage, physical video, audio and controls.
PC/XT foundation
MCL86 CPU, KFPC-XT chipset, conventional memory, optional UMB, EMS, BIOS, floppy drives and XTIDE.
Colour-compatible video
Native CGA timing, VRAM, text and graphics modes, simulated composite colour and a 320×200×4 graphical splash.
Monochrome video
Hercules-compatible text and graphics, available beside CGA, with a DDRAM converter for 15 kHz 480i or 240p television output.
CGA and HGC/MDA are independent hardware paths. The OSD can enable or disable their I/O, the BIOS selects the first display, and F11 changes the MiSTer output. The 15 kHz HGC/MDA conversion is output plumbing: DOS still sees the original card and timing.
Logical design
Core architecture
The design combines the CPU, chipset, memory and peripheral blocks with two clocked video subsystems. The MiSTer top level joins those blocks to SDRAM, DDRAM, the HPS, the OSD and the physical outputs.
Clock domains and ownership
The CGA path keeps its 14.31818 MHz-compatible raster. HGC/MDA has its own higher-rate processing clock and exposes a calibrated native stream. Cross-domain registers are synchronised at the output boundary, while the HGC/MDA framebuffer has explicit reset release and DDRAM arbitration.
Video I/O writes are stretched and acknowledged in the video clock domain, so short Max-speed CPU pulses do not lose CRTC or mode-register writes. The framebuffer reader has priority over capture because its line deadline is fixed; the writer publishes only complete, geometrically valid frames.
A television-compatible HGC/MDA raster does not change the emulated CRTC. Native output remains available for a display or scaler that accepts the source frequency; 480i and 240p are selected only when the output device needs 15 kHz.
Colour video
CGA: native timing and composite colour
The CGA path owns its VRAM aperture, CRTC/sequencer timing, attribute decoding, RGBI output and simulated composite decoder. It remains the stable reference raster for the boot splash and is not sent through the HGC/MDA framebuffer converter.
What the path contains
- CGA colour/text memory at the B8000h aperture.
- 6845-style character and graphics timing.
- Text, 320-wide and 640-wide graphics modes.
- RGBI palette and configurable monochrome presentation.
- Composite colour decoder with phase-aware timing.
Composite is part of the video path
When Composite video is enabled, RGBI transitions are decoded using the CGA colour burst and phase relationship. This is why the splash is rendered through CGA instead of being drawn as an unrelated overlay: it exercises the same active aperture and produces the same CRT/LCD colour behaviour.
The graphical boot splash
The bundled artwork is a 320×200 image quantised to four semantic colours and stored as packed 2-bit pixels. cga_splash_renderer.v expands each source pixel across the native CGA cadence and maps the four indices to the CGA palette. The palette mapping is calibrated separately for RGB and composite presentation.
Monochrome video
HGC/MDA: native card, television-ready output
HGC/MDA provides the monochrome text and Hercules graphics experience expected by DOS software. Its source picture is kept separate from CGA, including its memory aperture, CRTC timing, intensity handling and output selection.
Native path
- HGC/MDA memory at the B0000h/B8000h page selected by the card.
- 720-dot, 350-line-class source timing.
- Monochrome text with normal and bright intensity.
- Hercules-compatible 720×348 graphics behaviour.
- Independent HGC/MDA output and timing metadata.
15 kHz conversion
A 15 kHz television cannot display the HGC/MDA source raster progressively. The converter captures one complete frame in DDRAM and reads it out at a 910-dot, approximately 15.734 kHz raster. A published frame is never replaced halfway through the two fields.
480i keeps all source lines across two interlaced fields. 240p uses a stable progressive raster and selects a reduced active line set; it avoids interlace flicker at the cost of vertical detail.
Only hgc_fb_capture, hgc_fb_readout and hgc_ddr_arbiter use this path. Enabling 480i/240p has no effect on CGA.
Output controls
| OSD option | Effect | Use case |
|---|---|---|
Native | Leaves the source raster untouched. | Multisync display, scaler or compatible CRT. |
480i 15 kHz | Displays all source lines over two fields. | 15 kHz television with interlace. |
240p 15 kHz | Progressive output with reduced detail. | 15 kHz television where a steady picture is preferred. |
CRT H/V offset | Moves the converted raster. | Tube centring and overscan compensation. |
System capabilities
The machine around the video
The video paths are part of a complete PC/XT platform. The options below are built around the current config.tcl profile and source modules.
Processor and timing
- 8088 compatibility mode with a four-byte prefetch queue.
- 8086 mode with a six-byte queue and private 16-bit SDRAM path.
- 4.77 MHz, 7.16 MHz and 9.54 MHz cycle-counted settings.
- Max unthrottled profile for throughput testing.
- Fake 286 FLAGS option for reserved FLAGS-bit probes.
Memory and storage
- 640 KiB conventional memory and optional A0000h UMB.
- EMS up to 2 MiB with selectable C000h, D000h or E000h frame.
- Floppy A/B, IDE-backed hard-disk images and second SD.
- PCXT system BIOS and EC00h XTIDE option-ROM slots.
Audio
- AdLib OPL2 at 388h or the Sound Blaster FM-compatible address 228h.
- C/MS and optional Tandy SN76489-compatible audio.
- PC speaker and MIDI/MT32-pi bridge support.
Input and expansion
- PS/2 keyboard and mouse integration.
- Serial mouse on COM1 with a DOS driver such as CTMOUSE.
- Two analog or digital joysticks.
- MPU-401 UART at 330h–331h when MIDI is built.
Effective memory map
| Address | Size | Assignment | Notes |
|---|---|---|---|
00000h–9FFFFh | 640 KiB | Conventional SDRAM | DOS conventional memory. |
A0000h–AFFFFh | 64 KiB | Optional UMB | Controlled by the A000 UMB OSD option. |
B0000h–BFFFFh | 64 KiB | Video apertures | HGC/MDA page selection and CGA ownership determine the active view. |
C0000h–EFFFFh | 192 KiB | EMS / upper-memory overlays | Four 16 KiB banks through the selected frame. |
EC000h–EFFFFh | 16 KiB | XTIDE option ROM | Loaded from the EC00 BIOS slot when used. |
F0000h–FFFFFh | 64 KiB | PCXT system BIOS | Required for startup. |
Address space
PC/XT 1 MiB memory map
The CPU sees a 20-bit physical address space. The map below shows the normal overlays; video, EMS, UMB and option-ROM ownership depends on the build and on the OSD selections.
The map is an address-space view, not a promise that every block is simultaneously available as DOS UMB. The selected video card owns the B0000h/B8000h aperture, EMS takes its configured 16 KiB banks, and XTIDE occupies the EC00h option-ROM window when loaded.
| Address range | Size | Core assignment | DOS availability |
|---|---|---|---|
00000h–9FFFFh | 640 KiB | Conventional SDRAM | Conventional memory |
A0000h–AFFFFh | 64 KiB | Optional A000 UMB | UMB when enabled in the OSD |
B0000h–B7FFFh | 32 KiB | HGC/MDA video aperture, page 0 | Reserved for video when HGC/MDA is active |
B8000h–BFFFFh | 32 KiB | CGA colour/text aperture, or HGC/MDA page 1 | Reserved for the selected video path |
C0000h–EFFFFh | 192 KiB | EMS page-frame region; one 64 KiB frame is selected at C000h, D000h or E000h | EMS window, not conventional memory |
EC000h–EFFFFh | 16 KiB | XTIDE option-ROM window | Option ROM when the EC00 BIOS slot is loaded |
F0000h–FFFFFh | 64 KiB | PCXT system BIOS | Reserved for BIOS execution |
Effective configuration
OSD and build options
The OSD exposes the choices users need at runtime; config.tcl controls which optional hardware is compiled into an RBF.
Features in the default config.tcl
Blue chips are compiled into the default PCXT profile; red chips are defined but disabled. The optional Tandy system variant and its video, keyboard and audio paths are therefore excluded from this build.
| OSD group | Main available options |
|---|---|
| Disks | Floppy A/B, write protection, IDE images and second SD. |
| CPU | 4.77 MHz, 7.16 MHz, 9.54 MHz and Max. |
| System & BIOS | CGA/HGC enable, first video, splash, CPU type, Fake 286 FLAGS, PCXT BIOS, EC00 BIOS and write protection. |
| Audio & Video | OPL2/CMS, speaker, mixing, CRT offsets, sync widths, effects, aspect ratio, border, composite, display tint and HGC/MDA 350-line CRT mode. |
| Hardware | EMS, EMS frame, A000 UMB, joysticks, joystick swap and speed synchronisation. |
DOS environment
The supplied files are examples and must agree with the selected EMS frame and audio devices.
FILES=40; BUFFERS=30; DOS=HIGH,UMB; DEVICE=C:\UTIL\USE!UMBS.SYS D000-EC00; DEVICEHIGH=C:\UTIL\LTEMM.EXE /p:C000 /x /nGetting started
BIOS, splash and startup
Recommended path
- Copy
games/PCXTto the MiSTer SD card. - Select Computers / PCXT and open the OSD with Win + F12.
- Choose the model, CPU speed and 8088 or 8086 mode.
- Mount a floppy or hard-disk image.
- Load a compatible image into System & BIOS → PCXT BIOS.
- Use Reset & apply settings.
ROM roles
- PCXT BIOS occupies F0000h–FFFFFh and is required.
- EC00 accepts an XTIDE option ROM of up to 16 KiB.
- Some system BIOS images contain XTIDE at F0000h.
- BIOS choice determines floppy geometry and video assumptions.
- CGA and HGC/MDA initialise in the RTL paths; there is no separate video ROM requirement.
The core keeps the CGA splash visible, holds the machine in reset and exposes a notice pointing to System & BIOS → PCXT BIOS. This prevents an empty F0000h region from executing random data and keeps the OSD usable from the selected display.
F12 behaviour
F12 pauses the splash countdown and shows the JTFrame credits while the machine remains held. Pressing F12 again resumes the splash. After startup the same key pauses the machine and displays the credits. Win + F12 opens the MiSTer OSD.
Verification and boundaries
What is checked and what remains deliberate
Focused regression benches sit beside the RTL. They test the timing contracts easiest to break at Max or across video clock domains.
Regression areas
- 8086 SDRAM lookahead, wide transfers and byte-lane rules.
- RAM writes that overlap SDRAM refresh at Max.
- CGA VRAM wait and pixel/CRTC latency.
- Composite timing and colour-path behaviour.
- Graphical splash ROM stream and pixel cadence.
- F12 splash pause and missing-PCXT-BIOS hold.
- HGC framebuffer capture, readout, reset release and arbitration.
Known boundaries
- Max is an unthrottled throughput profile, not cycle-accurate historical hardware.
- 240p trades vertical detail for a stable progressive television picture.
- Native HGC/MDA requires a display or scaler that accepts its source frequency.
- BIOS and disk-image compatibility varies by firmware and media geometry.
- The core is not a general VGA, SVGA or host-emulator replacement.
Emulated PC/XT features remain software-visible in the chipset or video path. Physical-output conversion is kept after the native raster and does not feed back into CRTC state, VRAM or DOS-visible timing.
Project direction
What this core does and does not claim
Explicit goals
- Recreate a usable IBM PC/XT on MiSTer.
- Keep CGA and HGC/MDA behaviour understandable and independently testable.
- Make native CGA composite output useful on CRT and LCD displays.
- Make HGC/MDA usable on 15 kHz televisions as well as native-capable displays.
- Keep BIOS, OSD, splash and credits behaviour recoverable from the selected output.
Outside the current goal
- Complete VGA, SVGA or VBE compatibility.
- General-purpose PC emulation for every model and peripheral.
- Guaranteeing every BIOS, demo, disk image or CRT timing combination.
- Turning the HGC/MDA converter into a programmable scaler.
- Claiming that Max has the timing of a 4.77 MHz IBM motherboard.
Source layout
PCXT.sv | MiSTer top level, OSD, clocks, reset, storage, video selection and output. |
rtl/video/ | CGA, composite, HGC/MDA, scandoublers, splash and framebuffer converter. |
rtl/KFPC-XT/ | Chipset, CPU-facing bus, RAM, peripherals and testbenches. |
rtl/common/ | Shared support, credits, BIOS blocks and common memory. |
SW/ROMs/ | System BIOS and XTIDE preparation scripts. |
docs/ | Implementation notes, index and this report. |
Open project
Credits and licence
MiSTer integration and continuing project development by Aitor Gómez García (spark2k06), built on important contributions from the FPGA recreation and classic PC preservation communities.
The 8088/8086 CPU foundation comes from MCL86 by MicroCoreLabs, and the PC/XT chipset from KFPC-XT by kitune-san. The original CGA and Hercules-compatible video work includes the Graphics Gremlin project by TubeTimeUS. AdLib audio uses JTOPL by José Tejada; other audio, mouse, joystick, MIDI and MiSTer framework components retain their upstream credits. The complete in-core list is kept in credits/msg.
BoogerMann is explicitly acknowledged for contributions to the PCXT MiSTer development and collaboration around the project; the name is also retained in the in-core credits/msg list.
Technical contribution associated with BoogerMann: integration of the newer SystemVerilog MCL86 organisation, with separate BIU/EU, microcode and 8088-wrapper sources. It also carries the instruction-boundary INTR sampling fix (intr_delay), so maskable interrupt recognition remains deterministic across microcode timing and CPU speed profiles.
The repository is distributed under the GNU General Public License. Redistribution and modification must comply with that licence and the terms that apply to the integrated components.